用NOR做上機考

七段顯示器

用NAND畫出上機考

期中上機考(4input 1output)

Verilog程式碼(f為結構模式f0為行為模式)

module top;
system_clock #200 clock1(a);
system_clock #100 clock2(b);
system_clock #50 clock3(c);
system_clock #25 clock3(d);
many abc(f,f0,a,b,c,d);
endmodule

module many(f,f0,a,b,c,d);
input a,b,c,d;
output f,f0;
wire a_0,b_0,c_0,d_0,f1,f2,f3,f4,f5;
not(c_0,c);
not(a_0,a);
not(d_0,d);
not(b_0,b);
and(f1,a_0,b_0,d);
and(f2,a_0,b,c,d_0);
and(f3,a,b,d);
and(f4,a,c_0,d_0);
and(f5,a,b_0,d_0);
or(f,f1,f2,f3,f4,f5);
assign f0=((~a)&(~b)&d)|((~a)&b&c&(~d))|(a&b&d)|(a&(~c)&(~d))|(a&(~b)&(~d));
endmodule

module system_clock(clk);
parameter PERIOD=100;
output clk;
reg clk;
initial
clk=0;
always
begin
#(PERIOD/2)clk=~clk;
#(PERIOD-PERIOD/2)clk=~clk;
end
always@(posedge clk)if($time>1000)#(PERIOD-1)$stop;
endmodule

三輸入一輸出

AND邏輯閘